Technical FAQ

How does the P-ROC automatically scan switches?

There's a timer inside the P-ROC FPGA that expires every X ms, where X is configurable by software.  Each time the timer expires, the FPGA looks at all of the direct switch inputs, compares the current states with the previous states, and logs any state change.  After checking the direct switches, the FPGA steps through the switch matrix, strobing the appropriate column and then checking the corresponding rows.

There is a set of configuration registers corresponding to every switch input that is used to tell the FPGA how to identify a switch state change (debouncing) and what to do when a state change is detected.  For instance, the FPGA can be configured to notify the host when switch Y closes and is debounced.  The FPGA can also be configured to drive one or more output circuits (for coils/lamps/leds/motors/etc) when the switch Y event occurs.


How does the P-ROC automatically drive outputs?

The P-ROC FPGA has configuration registers for each of its 208 outputs that tell it how to drive each output.  Available driver modes include:

  • On/Off

The output is driven on or off until the configuration register is changed.

  • Timed drive

The output is driven for X number of milliseconds, where X is configurable.

  • Repeating schedules

The output is driven for one or more of 32 timeslots per second.  For instance, if is configured with a schedule of 0xaaaaaaaa, the output is driven for 31.25 ms, turned off for 31.25 ms, turned on for 31.25, etc because 1/32 of a second is 31.25 milliseconds.  Further, the entire schedule can run indefinitely by repeating every second, or it can be configured to automatically disable after X seconds.

  • Repeating pulse

The output is turn on for Y milliseconds and turned off for Z milliseconds, where Y and Z are configurable.  Once turned off for Z milliseconds, the cycle repeats

  • Timed drive followed by repeating pulse

This is a combination of two of the modes where the output is driven for X milliseconds after which it is repeatedly turned on for Y milliseconds and turned off for Z milliseconds.  This, for instance, could be used to drive a flipper coil that needs to be pulsed periodically to remain up with the flipper button is held in.

How does the P-ROC control a Dot Matrix Display?

The P-ROC FPGA has logic that reads dot data out of an internal memory and asserts the appropriate DMD control signals to send the dot data to the DMD.  The parameters for the DMD control signals are highly configurable allowing users to achieve varying framerates.

The internal memory can hold 4kB of data and should be filled by a PC application that generates the display information.  It is logically broken up into sub-frames, and the number of sub-frames is configurable up to 8.  When reading the dot data out of the memory, the FPGA logic will start at address 0, read the configured number of sub-frames, and then restart at address 0 again.


Can the P-ROC display varying brightness level pixels on a Dot Matrix Display?

Brightness levels are controlled by varying the time each dot is turn on.  This is typically done by dividing each display frame into multiple sub-frames.  The brightest dots would be on in all of the sub-frames while the dimmest dots would be on in only one of the sub-frames.  Since the FPGA can process up to 4 sub-frames, it's possible to have up to 16 brightness levels (2^4).


How many frames per second can be displayed on a Dot Matrix Display driven by a P-ROC?

The FPGA logic is highly configurable and can achieve over 200 fps, which is the maximum recommended by certain DMD vendors.  Since the human eye interprets around 25 - 30 frames per second as smooth, no more than that is really necessary.  Therefore, if the FPGA is configured to use 4-sub frames for brightness levels and to send 120 sub-frames to the DMD each second, the effective framerate is 120/4 or 30 fps.  In this example, to display fast moving video sequences, the PC application would need to fill the dot memory at least 30 times per second.


Will the P-ROC FPGA verilog source code be made available for download?

Not at this time, but the possibility is being considered.  Feel free to email This email address is being protected from spambots. You need JavaScript enabled to view it. if you have a need for the code.